DESIGN A PROCESSOR

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                   DESIGN A RISC PROCESSOR

I'm trying to give you another side of Computer Architecture.
This is limited functional processor.you can create this alogorthamcally.also you can
use test bench for testing input & outputs.




What is RISC? Actually it is called reduced instruction Set  Computer.
Also there are two types architectures.

1.ARM
2.MIPS


i'm going to design a processor using VERILOG VHDL in MIPS Architecture.

there are 7 milestones you have to achive to create Processor.

1.create 4 bit  bidirectional shift register using verilog.

 it is called as an Universal shift register.you can create it using 4 multiplexers(4:1) and 4 D- flip flops.i want to develop your own verilog code for that.

if you want more activities from this....please look below page.This is related to milestone 1.




// d flip flop module


module dFlipFlop(q, qbar, d, clk);
input d, clk;
output q, qbar;
if(clk == 1'b1)
begin
if(d == 1'b0) 
begin
q = 1'b0;
qbar = 1'b1;
end
else
begin
q = 1'b1;
qbar = 1'b0;
end
end
else qbar = ~q;
endmodule

above code using for design D-FlipFlop.Also you have to Create 4:1 Mux for that.



// 4 bit shift register module

module shiftReg4bit(out, shiftR, shiftL, load, s, enable);

input shiftR, shiftL; 
input [3:0]load; 
input [1:0]s;
output [3:0]out;
wire [3:0]i;
reg [3:0] q, qbar;
reg clk;
if(enable == 1'b1)
begin
if(s == 2'b00)  // holds the current value of the register
begin
clk = 1'b0;
dFlipFlop d0(q[0], qbar[0], q[0], clk);
dFlipFlop d1(q[1], qbar[1], q[1], clk);
dFlipFlop d2(q[2], qbar[2], q[2], clk);
dFlipFlop d3(q[3], qbar[3], q[3], clk);
assign out = q;
end
else if(s == 2'b01) // loads the register
begin
clk = 1'b1;
dFlipFlop d0(q[0], qbar[0], load[0], clk);
dFlipFlop d1(q[1], qbar[1], load[1], clk);
dFlipFlop d2(q[2], qbar[2], load[2], clk);
dFlipFlop d3(q[3], qbar[3], load[3], clk);
assign out = q;
end
else if(s == 2'b10)  // left shifts the current value of the register by one bit
begin
clk = 1'b1;
dFlipFlop d3(q[3], qbar[3], out[2], clk);
dFlipFlop d1(q[2], qbar[2], out[1], clk);
dFlipFlop d2(q[1], qbar[1], out[0], clk);
dFlipFlop d3(q[0], qbar[0], shiftL, clk);
assign out = q;
end
else if(s == 2'b11) // right shifts the current value of the register by one bit
begin
clk = 1'b1;
dFlipFlop d0(q[0], qbar[0], out[1], clk);
dFlipFlop d1(q[1], qbar[1], out[2], clk);
dFlipFlop d2(q[2], qbar[2], out[3], clk);
dFlipFlop d3(q[3], qbar[3], shiftR, clk);
assign out = q;
end
end

endmodule



next time will be Milestone 2. Thank You.

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